Features of Schemata
- Unlimited undo and re-do.
- Wires can be drawn through devices and break appropriately,
they break when devices are added on to them and re-connect when devices
- Devices can be copied, flipped and connected in one
- Moving devices or wires moves other connected
devices to maintain a “nice” drawing.
- Selected areas may be cut, copied, flipped and
rotated in one operation.
- All text is editable in-place and intelligent
completion is supported.
- Multiple instances may be edited in one operation.
- All schematic elements are independently placed and
not in a fixed relation to the symbol – all text is “nudge-able”, all
symbols are independent – one FET need not be draw like another (the
symbol object is copied into the schematic and becomes independently
- Symbols are created automatically, often needing no
- Multiple different symbols may represent the same
- Wires may pass in and out of symbols – no
restriction on the number of repeated connections.
- Transparent symbols are supported, allowing the
contents to be visible at the higher levels.
- Regular and transparent symbols can be iterated and
connected with buses.
- Net names, directions and port status are “guessed”
from the schematic context often needing no further editing.
- One mouse click attaches wires and names all ports
on a symbol.
- Bus syntax supports binary connections: for
example, 64 repeated instances of a six input gate may easily be connected
to make a decoder, the bus being connected appropriately.
- Bus syntax includes rotation operations, repeat
operations and bus merging
- Merged devices can be indicated and the netlist
adjusts appropriately to show the different capacitances that result from
- A net may have multiple names.
- Globals from lower levels
may be easily “captured” and converted to local or ports, allowing
differing power supplies to be used in logic blocks that share the same
named globals. (This is perhaps the most useful feature of all Schemata
capabilities – Global nets behave like global names in the PASCAL
programming language – it means that you can use one logic library with
global VDD/GND and yet still connect these global nets to different power
- Primitive devices have default connections that
automatically connect to the appropriate well/substrate nodes so that only
“3 port” CMOS devices are needed. In cases where a specific device has a
different well/substrate its optional connection may be used – this
considerably clarifies analog schematics.
- Parameters on devices may be based on arithmetic
operations of parameters on other devices, or on parameters passed into
the circuit or on parameters associated with the current process so that
process-independent schematics can be created.
- One click and drag operation created “extra space”
in the drawing to maintain a neat schematic when new devices must be
- One click “compresses” the drawing to remove unused
space on the page.
- Macro models may represent any schematic and
multiples instances of the same schematic at a lower level may be used as
macros or as expanded schematics allowing evaluation of a complex
schematic on an instance by instance basis.
- Node voltages and currents (from SPICE) may be
annotated onto the schematic.
- One click operation initiates plotting of voltages on
wires, current through ports, noise variance vs time and noise spectral
- Parameters of the devices, dc operating points and
noise may be tabulated, sorted and dumped to Excel files.
- Clicking on any table entry finds the corresponding
device anywhere in the hierarchy and brings that device, in that context,
- Post layout netlists (R, C or RC) can be used on an
instance by instance basis to check out effects of layout capacitance and
trace resistance; complete click and plot is supported, (including the
voltages on newly inserted nodes in the RC extract, the names of which are
calculated from the port that the user click on) .
- In post layout mode any node capacitance can be
- Elements of the schematic may be notated as “simulation
only” to exist in the simulation netlist, not the LVS netlist, allowing
simulation sources etc to remain in the schematic and yet not affect the
- Complex post processing in the graphic window
analyses frequency and jitter, calculates VCO K factors, IP3-like plots,
linearity, advanced FFT techniques, audio noise measurements (A-weighted
etc) settling time of DACS, open-loop (UGB, Phase margin etc) and a great
- The graph plotter reads Excel data, CSV tabulated
data, Audio precision files, oscilloscope data files and many more to
allow simulation vs lab-result comparisons.
- The graphs support left, top, right and bottom axis
in any combinations, in log, linear, percent and time formats.
- Drag and drop one trace to another window, zoom in,
annotate and print.
- Multiple graph window formats are supported -
shared/unshared axes, square and linear arrangements abutted or spaced,
and many other formats.
- Graphs, tables, schematics and comments may be
collected into a Wiki (DokuWiki
is the one supported) with just one click allowing documentation as the
- In the Wiki actual data is attached – at any time
later a click on the objects in the browser window finds the data and
loads it up into either the schematic or graph plotter as appropriate.
- Scripts can change the process corners, initiate
SPICE simulations and document results directly into the Wiki.
- A built-in mailer can send a complete design to a
colleague in just one click.
- Schemata is integrated with MS Windows – it uses
the clipboard to send drawings to Paint and Word etc and data to Excel.
- Schematics may be printed with bitmaps indicating
company or project logos.
- Schematics are locked on the network to prevent
multiple changes, user groups and individual users may lock on a directory
by directory basis. An attempt to edit a locked schematic allows edit but
not saving to the same file.
- A schematic “diff” operation is provided that
visually compares two schematics side by side and indicates any
- You may at any time compare your work to the latest
- Simulation scripts are part of the schematic and
saved with it.
- One-click re-runs any simulations that the designer
has performed to easily re-check results or to easily re-simulate after
the post layout netlist has been extracted.
- One-click changes process corners.
- One-click changes the design into any of the
supported processes – no change to the schematic is need when the process
is changed. Even device geometries are adjusted if, in the initial design,
the user has used the process derived variables (such as nlogw which is
the Nmos Logic Width and many others) or has used the process case
selector for the parameters (for example, if GSMC015 10k if TSMC018 3k
means if a Grace Semiconductor 150nm process is being used the value is
10k, if a TSMC 180nm process is being used the value is 3k).
- The schematic writes netlist files for Spice and
for LVS (which may differ since elements can be marked as “simulation
- Verilog netlists correctly indented, correctly
using buses where appropriate and correctly defining I/O are can be
written out to support a Verilog netlist driven back-end chip assembly.
- Schemata supports IO pads that define bond pad
order and pin number, the pin out table is dynamically generated and an
Excel file of the pin out including pin descriptions for data sheet
generation is created.
- A “distribution” features is provided to collect all
components, including any simulation scripts and results, into a compact “zip-like” file
in order to archive or send a complete design to another user or another
- Graphical results, Excel spreadsheet and arbitrary
other files may be associate with a schematic to become part of the
- A drag and drop outline allows hierarchical
renaming and hierarchical re-arranging to be done easily.
- Consistency checking tools allow all schematic
sources to be verified as coming from the appropriate libraries and file.
- “Logical Pathnames” (somewhat like libraries)
abstract the schematic design from the file system allowing designs to be
easily copied or moved to another site, another disk or USB stick.
- An unpacking feature shows any version changes visually
in a side by side comparison if a similarly named circuit exists at
another computer or site so allowing unpacking of a large hierarchical
design without accidentally overwriting a local schematic that happens to
have the same name in the same library, or any later revision of a
schematic not used in the distribution received..
- One click archive backs up all schematics.
- A search feature searches all schematics at a site
by name, by any simulation script entry or by any macro model.
- Schemata supports Excel as a schematic data source
to allow complex interconnected analog cells to be parameterized and
interconnected from a definition developed in an Excel spread sheet. This
unusual capability allows the designer to interconnect tens of thousands of
minimum sized transistors in innovative ways to create analog cells that
operate as “systolic arrays” achieving functionality through
interconnection patterns. Schemata reads the Excel file directly (using MS
OLE) and automatically translates it into a netlist for SPICE. One mouse
click activates the Excel file feature – no programming needed.