Using Schemata with a Post-Layout Netlists

Using the Post Layout Netlist for verification (ie for simulation) is essential for high performance and/or small CMOS geometries - only the post-layout netlist has the accurate capacitances on the nodes. The Schemata tool can integrate the post-layout netlist into your design so that any netlists you have for layed-out circuits can be used. When you use the post layout netlist with the Schematic tool you can probe the capacitance on nets in your design and you can probe the voltages on the terminals of individual devices (the terminal voltages on the nodes are not necessarily the same since the post layout netlist will model the metal routing resistances)

How to use the Post Layout Netlist with Schemata

Release 4.3.97 and later adds an ability to simulate and probe a design where part of the hierarchy is already laid out and has a Star-RC extracted netlist. Here is a brief description of how to go about using that post-layout extraction in the Schematic:

† 1) Copy the post layout files into the same directory (the same LPN) as the schematic that it represents - so, for example, if your schematic is called "MySchematics:Fred;SDdesign.sch" bring up that design in the schematic. Right click on the Directory in the "Schematics" outline - thatís the middle tab in the top left window - and choose "Show Directory" (tip: to find the directory in the Schematics outline you can click right on the tab with the schematic name and choose "Show Definition in Schematic Outline")

† 2) You must rename the post-layout files to be <schem-name>_RC_typ.sp, <schem-name>_RC_max.sp, <schem-name>_RC_min.sp. So for example, if your schematic is called "MySchematics:Fred;SDdesign.sch" then these files, given to you by the layout engineer, should be named "SDesign_RC_typ.sp" "SDesign_RC_max.sp" and "SDesign_RC_min.sp".

† 3) While editing the Schematic that has the layout netlist (ie SDesign.sch in this example) open the "Spice Macro" outline on the top right and then open the process that was used for the layout. (SMIC15 for example). In the note window (thats the white box at the top where you write simulation scripts etc) insert the following LISP form: "(netlist-from-post-layout-file)" without the ". (tip: to help you, you can click right on the window and choose "Netlist From Post Layout File" and this will insert the form for you).

† 4) Now go to the schematic that you wish to simulate, presumably one that at some point calls for the schematic that has been laid out. Push into any schematics as required until you see the USE of the schematic that has the layout (note the USE meaning the box that says something like "U1" and "SDesign" on it). Click right on this use and choose "Spice Macro Model On/Off". When the macro model is enabled the use will have a grey background. You have just instructed this particular use to use the post layout netlist. (Note you can have another use of the same name that does, or does not, use the post layout netlist).

† 5) Run the simulation. The SPICE deck will have a call to the slightly modified netlist (the modification is automatic and creates an include file of type "pl-netlist" if you care to look at it).

† 6) After the simulation you can probe voltages on wires, currents etc. But now two new features are possible:

††† a) You may probe the voltage exactly on the port of a primitive device - at the drain of M1 for example, and this may not be the identical voltage as on the gate of M2 to which it connects. To probe the voltage on a port, click right on the small box that appears when the mouse is near a port and choose "Plot Post Layout Voltage" (or "Add Post Layout Voltage" which adds the voltage trace to the current plot)

†† †b) You may now probe the layout capacitances (as well as the voltages and currents). To do this activate layout flags (the small "L" button one, so it becomes blue) and then Update Labels (ie click the S with green arrow). Any DC probes you have will then become light blue and show the node capacitances. To get the DC voltages/currents simply turn off layout flags and click the Update Labels button again. (You can see how this works: you add the flags first, typically in voltage/current mode - then when you enable layout flags and update labels the flags become the capacitance values).

† 7) Finally, if you change the process corners, the Schematic includes the correct post-layout file - you should not have to manually do anything.